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19-3979; Rev 0; 2/06
Overvoltage-Protection Controllers with Status FLAG
General Description
The MAX4838A/MAX4840A/MAX4842A are overvoltageprotection ICs that protect low-voltage systems against voltages of up to +28V. If the input voltage exceeds the overvoltage trip level, the MAX4838A/MAX4840A/ MAX4842A turn off the low-cost external n-channel FET(s) to prevent damage to the protected components. An internal charge pump eliminates the need for external capacitors and drives the FET gate for a simple, robust solution. The MAX4838A has a 7.4V overvoltage threshold, and the MAX4840A has a 5.8V overvoltage threshold. The MAX4842A has a 4.7V overvoltage threshold. The MAX4838A/MAX4840A have an undervoltage-lockout (UVLO) threshold of 3.25V, while the MAX4842A has a UVLO of 2.5V. In addition to the single FET configuration, the devices can be configured with back-to-back external FETs to prevent currents from being back-driven into the adapter. On power-up, the device waits for 50ms before driving GATE high. FLAG is held low for an additional 50ms after GATE goes high before deasserting. The MAX4838A/MAX4840A/MAX4842A have an open-drain FLAG output. The FLAG output asserts immediately to an overvoltage fault. Additional features include a 15kV (HBM) ESD-protected input (when bypassed with a 1F capacitor) and a shutdown pin (EN) to turn off the device. All devices are offered in a small 6-pin SC70 and 6-pin 1.5mm x 1.0mm DFN packages and are specified over the -40C to +85C extended temperature range. Overvoltage Protection Up to +28V Preset 7.4V, 5.8V, or 4.7V Overvoltage Trip Level Drives Low-Cost nMOS FET Internal 50ms Startup Delay Internal Charge Pump Undervoltage Lockout 15kV ESD-Protected Input Voltage Fault FLAG Indicator 6-Pin SC70 and DFN Packages Lead Free
Features
MAX4838A/MAX4840A/MAX4842A
Ordering Information
PART MAX4838AEXT+T MAX4838AELT+ MAX4840AEXT+T MAX4840AELT+ MAX4842AEXT+T MAX4842AELT+* PINPACKAGE 6 SC70 6 DFN 6 SC70 6 DFN 6 SC70 6 DFN TOP MARK ACY KU ACZ KV ADA KW PKG CODE X6S-1 L611-1 X6S-1 L611-1 X6S-1 L611-1
Note: All devices specified for the -40C to +85C extended temperature range. *Future product--contact factory for availability. +Denotes lead-free package.
Applications
Cell Phones Digital Still Cameras PDAs and Palmtop Devices MP3 Players
INPUT +1.2V TO +28V
Typical Operating Circuit
OUTPUT NMOS 1 IN GATE 4 VIO
Selector Guide
PART OV UVLO TRIP EN THRESHOLD LEVEL INPUT (V) (V) 3.25 3.25 2.50 7.4 5.8 4.7 Yes Yes Yes FLAG OUTPUT Open-Drain Open-Drain Open-Drain
1F
6 EN 2
MAX4838A MAX4840A MAX4842A
FLAG 3 NOTE: EN AND PULLUP RESISTOR
GND
MAX4838A MAX4840A MAX4842A
Pin Configuration appears at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
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Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
ABSOLUTE MAXIMUM RATINGS
IN to GND ..............................................................-0.3V to +30V GATE to GND ........................................................-0.3V to +12V EN, FLAG to GND ....................................................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 6-Pin SC70 (derate 3.1mW/C above +70C) .............245mW 6-Pin DFN (derate 2.1mW/C above +70C) ............477mW Operating Temperature Range ..........................-40C to +85C Junction Temperature .................................................... +150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Voltage Range Undervoltage-Lockout Threshold Undervoltage-Lockout Hysteresis VIN rising Overvoltage Trip Level OVLO VIN rising VIN rising MAX4838A MAX4840A MAX4842A No load, EN = GND or 5V, VIN = 5V (MAX4838A/MAX4840A) No load, EN = GND or 4.0V, VIN = 4V (MAX4842A) VIN = 2.9V (MAX4838A/MAX4840A) VIN = 2.2V (MAX4842A) IGATE sourcing 1A MAX4838A/MAX4840A MAX4842A 1.2V VIN < UVLO, ISINK = 50A VIN OVLO, ISINK = 1mA 1.5 0.4 EN = GND or 5.5V 1 9 7.5 27 0.4 V 0.4 1 A V V A MAX4838A MAX4840A MAX4842A 7.0 5.5 4.4 SYMBOL VIN UVLO VIN falling MAX4838A/MAX4840A MAX4842A CONDITIONS MIN 1.2 3.0 2.3 3.25 2.5 50 7.4 5.8 4.7 100 80 50 80 75 200 A 160 30 22 10 8.0 mA A V 7.8 6.1 5.0 V TYP MAX 28.0 3.5 2.7 UNITS V V mV
Overvoltage Trip Level Hysteresis
mV
IN Supply Current
IIN
UVLO Supply Current GATE Voltage GATE Pulldown Current
IUVLO VGATE IPD
VIN > VOVLO, VGATE = 5.5V
FLAG Output Low Voltage
VOL
FLAG asserted
FLAG Output High Leakage EN Input High Voltage EN Input Low Voltage EN Input Leakage
IOH VIH VIL ILKG
VFLAG = 5.5V, FLAG deasserted
2
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Overvoltage-Protection Controllers with Status FLAG
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A), TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER TIMING Startup Delay FLAG Blanking Time GATE Turn-On Time tSTART tBLANK tGON VIN > VUVLO, VGATE > 0.3V, Figure 1 VGATE > 0.3V, VFLAG > 2.4V, Figure 1 VGATE = 0.3V to 8V (MAX4838A/MAX4840A), VGATE = 0.3V to 6V (MAX4842A), CGATE = 1500pF, Figure 1 VIN increasing from 5V to 8V at 3V/s (MAX4838A/MAX4840A), VIN increasing from 4V to 6V at 3V/s (MAX4842A), VGATE = 0.3V, CGATE = 1500pF, Figure 2 VIN increasing from 5V to 8V at 3V/s (MAX4838A/MAX4840A), VIN increasing from 4V to 6V at 3V/s (MAX4842A), VFLAG = 0.4V, Figure 2 VIN increasing from 0 to 8V (MAX4838A/MAX4840A), VIN increasing from 0V to 6V (MAX4842A), IGATE = 80% of IPD, Figure 3 VEN = 2.4V, VGATE = 0.3V, Figure 4 20 20 50 50 10 80 80 ms ms ms SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX4838A/MAX4840A/MAX4842A
GATE Turn-Off Time
tGOFF
6
20
s
FLAG Assertion Delay
tFLAG
5.8
s
Initial Overvoltage Fault Delay
tOVP
1.5
s
Disable Time
tDIS
2
s
Note 1: All parts are 100% tested at +25C. Electrical limits across the full temperature range are guaranteed by design and correlation.
Typical Operating Characteristics
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A); Si9936DY external MOSFET in back-to-back configuration; TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. INPUT VOLTAGE
MAX4838A toc01
REVERSE CURRENT vs. OUTPUT VOLTAGE
MAX4838A toc02
MAX4838A/MAX4840A GATE VOLTAGE vs. INPUT VOLTAGE
MAX4838A toc03
600 500 SUPPLY CURRENT (A) 400 300 200 100 0 0 5 10 15 20 25
1000 SINGLE MOSFET REVERSE CURRENT (A) 100
12
9 GATE VOLTAGE (V)
10
6 MAX4840A 3 MAX4838A
1
BACK-TO-BACK MOSFETS
0.1 30 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
0 3 4 5 6 7 8 INPUT VOLTAGE (V)
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3
Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
Typical Operating Characteristics (continued)
(VIN = +5V (MAX4838A/MAX4840A), VIN = +4V (MAX4842A); Si9936DY external MOSFET in back-to-back configuration; TA = +25C, unless otherwise noted.)
MAX4842A GATE VOLTAGE vs. INPUT VOLTAGE
MAX4838A toc04
GATE VOLTAGE vs. INPUT VOLTAGE
MAX4838A toc05
MAX4838A/MAX4840A POWER-UP RESPONSE
MAX4838A toc06
12
11.0 IGATE = 0 10.5 GATE VOLTAGE (V) IGATE = 4A
9 GATE VOLTAGE (V) MAX4842A 6
5V 0V 10V
IN
GATE
10.0
IGATE = 8A
0V 5V OUT
3
9.5
0V 5V ROUT = COUT = 0 20ms/div FLAG
0 0 1 2 3 4 5 6 7 8 INPUT VOLTAGE (V)
9.0 5.0 5.1 5.2 5.3 5.4 5.5 INPUT VOLTAGE (V)
MAX4838A/MAX4840A POWER-UP RESPONSE
MAX4838A toc07
MAX4842A POWER-UP RESPONSE
MAX4838A toc08
MAX4842A POWER-UP RESPONSE
MAX4838A toc09
5V IN 0V 10V 0V 1A IIN 0A 5V 0V 20ms/div ROUT = 5 FLAG GATE
4V 0V 8V
IN
4V 0V 8V
IN
GATE 0V 4V 0V 4V 0V OUT ROUT = COUT = 0 20ms/div FLAG 0V 800mA 0A 4V 0V
GATE
IIN ROUT = 5 FLAG
20ms/div
OVERVOLTAGE RESPONSE
MAX4838A toc10
POWER-UP OVERVOLTAGE RESPONSE
MAX4838A toc11
POWER-DOWN RESPONSE
MAX4838A toc12
8V 5V 10V 0V 40mA
IN
8V 0V GATE PULLED UP TO IN WITH 100
IN
5V 0V 10V
RLOAD = 50 RFLAG = 100k TO +5V
IN
GATE
5V GATE 0V 50mA IGATE
GATE 0V 5V OUT 0V 5V FLAG 0V 10ms/div
0A 5V 0V CGATE = 1500pF 400ns/div
IGATE FLAG
0A 5V FLAG 0V 1s/div
4
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Overvoltage-Protection Controllers with Status FLAG
Pin Description
PIN 1 2 3 4 5 6 NAME IN GND FLAG GATE N.C. EN FUNCTION Input. IN is both the power-supply input and the overvoltage sense input. Bypass IN to GND with a 1F capacitor or larger. Ground Fault Indication Output, Open-Drain, Active Low. FLAG is asserted low during undervoltagelockout and overvoltage-lockout conditions. FLAG is deasserted during normal operation. Gate-Drive Output. GATE is the output of an on-chip charge pump. When VUVLO < VIN < VOVLO, GATE is driven high to turn on the external n-channel MOSFET(s). No Connection. Not internally connected for DFN package. Connected to ground for SC70 6-pin package; connect to ground or leave unconnected. Device Enable Input, Active Low. Drive EN low or connect to ground to allow normal device operation. Drive EN high to turn off the external MOSFET.
MAX4838A/MAX4840A/MAX4842A
Timing Diagrams
VIN 0V 5V (4V) VUVLO tGON 8V (6V) tSTART VGATE 0.3V tBLANK VFLAG ( ) MAX4842A 2.4V VFLAG 0.4V ( ) MAX4842A VGATE 0.3V VIN 5V (4V) tGOFF 8V (6V) VOVLO tFLAG
Figure 1. Startup Timing Diagram
Figure 2. Shutdown Timing Diagram
VIN 0V
8V (6V) VOVLO tOVP 80%
VEN
1.5V tDIS
VGATE
IGATE
0.3V
( ) MAX4842A
Figure 3. Power-Up Overvoltage Timing Diagram
Figure 4. Disable Timing Diagram
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5
Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
IN GND
5.5V REGULATOR
2x CHARGE PUMP
GATE DRIVER
GATE
UVLO AND OVLO DETECTOR EN
CONTROL LOGIC AND TIMER MAX4838A MAX4840A MAX4842A
FLAG
Figure 5. Functional Diagram
Detailed Description
The MAX4838A/MAX4840A/MAX4842A provide up to +28V overvoltage protection for low-voltage systems. When the input voltage exceeds the overvoltage trip level, the MAX4838A/MAX4840A/MAX4842A turn off a low-cost external n-channel FET(s) to prevent damage to the protected components. An internal charge pump (Figure 5) drives the FET gate for a simple, robust solution.
GATE Driver
An on-chip charge pump is used to drive GATE above IN, allowing the use of low-cost n-channel MOSFETS. The charge pump operates from the internal 5.5V regulator. The actual GATE output voltage tracks approximately two times VIN until VIN exceeds 5.5V or the OVLO trip level is exceeded, whichever comes first. The MAX4838A has a 7.4V typical OVLO; therefore GATE remains relatively constant at approximately 10.5V for 5.5V < VIN < 7.4V. The MAX4840A has a 5.8V typical OVLO, but this can be as low as 5.5V. The MAX4840A in practice may never actually achieve the full 10.5V GATE output. The MAX4842A has a 4.7V (typ) OVLO, and the GATE output voltage is 2x the input voltage. The GATE output voltage as a function of input voltage is shown in the Typical Operating Characteristics.
Undervoltage Lockout (UVLO)
The MAX4838A/MAX4840A have a fixed 3.25V typical undervoltage-lockout level (UVLO) while the MAX4842A has a 2.5V typical UVLO. When VIN is less than the UVLO, the GATE driver is held low and FLAG is asserted.
Overvoltage Lockout (OVLO)
The MAX4838A has a 7.4V typical overvoltage threshold (OVLO), and the MAX4840A has a 5.8V typical overvoltage threshold. The MAX4842A has a 4.7V typical overvoltage threshold. When VIN is greater than OVLO, the GATE driver is held low and FLAG is asserted.
Device Operation
The MAX4838A/MAX4840A/MAX4842A have an onboard state machine to control device operation. A flowchart is shown in Figure 6. On initial power-up, if VIN < UVLO or if VIN > OVLO, GATE is held at 0V, and FLAG is low. If UVLO < VIN < OVLO and EN is low, the device enters startup after a 50ms internal delay. The internal charge pump is enabled, and GATE begins to be driven above VIN by the internal charge pump. FLAG is held low during startup until the FLAG blanking period expires, typically 50ms after the GATE starts going high. At this point the device is in its on state. At any time if VIN drops below UVLO, FLAG is driven low and GATE is driven to ground.
FLAG Output
The FLAG output is used to signal the host system there is a fault with the input voltage. FLAG asserts immediately to an overvoltage fault. FLAG is held low for 50ms after GATE turns on before deasserting. All devices have an open-drain FLAG output. Connect a pullup resistor from FLAG to the logic I/O voltage of the host system.
EN Enable Input
EN is an active-low enable input. Drive EN low or connect to ground to enable normal device operation. Drive EN high to force the external MOSFET(s) off. EN does not override an OVLO or UVLO fault.
6
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Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
STANDBY GATE = 0 FLAG = LOW VIN > UVLO
1F INPUT 0 TO 28V NMOS OUTPUT
1
IN
GATE
4 VIO
VIN < UVLO
TIMER STARTS COUNTING t = 50ms OVLO CHECK GATE = 0 FLAG = LOW VIN < OVLO STARTUP GATE DRIVEN HIGH FLAG = LOW t = 50ms ON GATE HIGH FLAG = HIGH VIN > OVLO
6 EN 2
MAX4838A MAX4840A MAX4842A
FLAG GND 3
NOTE: EN AND PULLUP RESISTOR ON MAX4838A/ MAX4840A/MAX4842A ONLY.
Figure 7. Back-to-Back External MOSFET Configuration
3.5V, consider using a MOSFET specified for a lower VGS voltage. Also, the VDS should be 30V for the MOSFET to withstand the full 28V IN range of all devices. Table 1 shows a selection of MOSFETs appropriate for use with the MAX4838A/MAX4840A/MAX4842A.
IN Bypass Considerations
For most applications, bypass IN to GND with a 1F ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit and provide protection if necessary to prevent exceeding the 30V absolute maximum rating on IN. The MAX4838A/MAX4840A/MAX4842A provide protection against voltage faults up to 28V, but this does not include negative voltages. If negative voltages are a concern, connect a Schottky diode from IN to GND to clamp negative input voltages.
Figure 6. State Diagram
Applications Information
MOSFET Configuration
The MAX4838A/MAX4840A/MAX4842A can be used with either a single MOSFET configuration as shown in the Typical Operating Circuit, or can be configured with a back-to-back MOSFET as shown in Figure 7. The back-to-back configuration has almost zero reverse current when the input supply is below the output. If reverse current leakage is not a concern, a single MOSFET can be used. This approach has half the loss of the back-to-back configuration when used with similar MOSFET types, and is a lower cost solution. Note that if the input is actually pulled low, the output is pulled low as well due to the parasitic body diode in the MOSFET. If this is a concern, then the back-to-back configuration should be used.
ESD Test Conditions
ESD performance depends on a number of conditions. The MAX4838A/MAX4840A/MAX4842A are specified for 15kV typical ESD resistance on IN when IN is bypassed to ground with a 1F ceramic capacitor. Contact Maxim for a reliability report that documents test setup, methodology, and results.
Human Body Model
Figure 8 shows the Human Body Model, and Figure 9 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5k resistor.
MOSFET Selection
The MAX4838A/MAX4840A/MAX4842A are designed for use with either a single n-channel MOSFET or dual backto-back n-channel MOSFETs. In most situations, MOSFETs with RDS(ON) specified for a VGS of 4.5V work well. If the input supply is near the UVLO maximum of
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7
Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
Table 1. MOSFET Suggestions
PART Si5902DC Si1426DH FDC6305N FDC6561AN FDG315N CONFIGURATION/ PACKAGE Dual/1206-8 Single/SC70-6 Dual/SSOT-6 Dual/ SSOT-6 Single/SC70-6 VDS MAX (V) 30 30 20 30 30 RON AT 4.5V (m) 143 115 80 145 160 MANUFACTURER Vishay Silconix www.vishay.com 402-563-6866 Fairchild Semiconductor www.fairchildsemi.com 207-775-8100
IEC 61000-4-2
Since January 1996, all equipment manufactured and/or sold in the European community has been required to meet the stringent IEC 61000-4-2 specification. The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX4838A/MAX4840A/ MAX4842A help users design equipment that meets Level 3 of IEC 61000-4-2, without additional ESD-protection components. The main difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2. Because series resistance is lower in the IEC 61000-4-2 ESD test model (Figure 10),
the ESD-withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 11 shows the current waveform for the 8kV IEC 61000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charger probe. The Contact Discharge method connects the probe to the device before the probe is energized.
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST IP 100% 90% AMPERES Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Cs 100pF
STORAGE CAPACITOR
36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM
Figure 8. Human Body ESD Test Model
Figure 9. Human Body Model Current Waveform
8
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Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
I 100% RC 50 to 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST 90%
Cs 150pF
STORAGE CAPACITOR
I PEAK
10% t r = 0.7ns to 1ns t 30ns 60ns
Figure 10. IEC 61000-4-2 ESD Test Model
Figure 11. IEC 61000-4-2 ESD Generator Current
Pin Configurations
PROCESS: BiCMOS
TOP VIEW
+ IN 1 6 EN
Chip Information
GND 2
MAX4838A MAX4840A MAX4842A
5
N.C.
FLAG 3
4
GATE
SC70
TOP VIEW
+ IN 1 6 EN
GND 2
MAX4838A MAX4840A 5 N.C. MAX4842A
4 GATE
FLAG 3
DFN
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9
Overvoltage-Protection Controllers with Status FLAG MAX4838A/MAX4840A/MAX4842A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6L UDFN.EPS
TABLE1 Translation Table for Calendar Year Code Calendar Year 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 Legend: Marked with bar Blank space - no bar required TABLE2 Translation Table for Payweek Binary Coding Payweek 06-11 12-17 18-23 24-29 30-35 36-41 42-47 48-51 52-05 Legend: Marked with bar Blank space - no bar required
TITLE:
PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm
APPROVAL DOCUMENT CONTROL NO. REV.
-DRAWING NOT TO SCALE-
21-0147
D
2
2
10
______________________________________________________________________________________
Overvoltage-Protection Controllers with Status FLAG
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
SC70, 6L.EPS
MAX4838A/MAX4840A/MAX4842A
PACKAGE OUTLINE, 6L SC70
21-0077
C
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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